1. Field of the Invention
The present invention relates to a latency counter, which is applied to a memory, and more particularly relates to a latency counter having a frequency detector, and a method thereof.
2. Description of the Prior Art
In recent times, random access memory (RAM) has become an increasingly important component in modern electronic devices. In order to increase the writing/reading data rate of the random access memory (RAM), the technique of double data rate (DDR) has become more and more important. A random access memory that utilizes the technique of double data rate is known as a double data rate random access memory (DDR RAM). Normally, when a microprocessor is ready to access a memory, the microprocessor transmits a reading signal to the control circuit of the memory, wherein the reading signal is synchronized with an external clock. In addition, according to prior art, a latency counter is coupled between the microprocessor and the control circuit, for providing a delay time (delay clock period number) to the reading signal in order to guarantee that there is enough time for the memory to access the specific address. Furthermore, because of the wide operating frequency range of the memory, the latency counter needs to have a different delay clock period number at a high operating frequency from that at a low operating frequency. In other words, when operating at the high operating frequency, the delay clock period number should be larger, but when operating at the low operating frequency, the delay clock period number should be smaller. However, the intrinsic delay of the circuit will affect the synchronization between the external clock and the reading signal. In other words, when operating at the high operating frequency, the intrinsic delay of the circuit may be higher than the clock period of the high operating frequency; thus the latency counter may output an error latency delay when the reading signal has slight non-synchronicity with the external clock, and the control circuit will read the error signal consequently. Furthermore, the latency counter designed for being utilized at a high memory operating frequency having a larger delay period number is not appropriate to be used at a low memory operating frequency having a smaller delay period number.